This invention relates to electrical logic circuitry. More particularly, it is concerned with logic circuits which provide an interface between two logic systems.
Two widely-used, well-known logic systems are ECL (emitter coupled logic) and CMOS (complementary metal oxide semiconductor) logic systems. The logic levels for ECL logic are -1.6 volts and -0.8 volt and for CMOS the logic levels are 0 volts and +5 volts. The threshold voltage for CMOS logic, that is the voltage at which a CMOS logic circuit triggers from one operating state to another, is +2.5 volts. Since this voltage is outside the operating range of ECL logic, CMOS logic circuitry is not directly compatible with ECL circuitry. CMOS logic circuits may be made compatible with input from ECL circuitry by changing the operating voltages of the CMOS circuitry to -3.7 volts and +1.3 volts to provide a threshold voltage of -1.2 volts, the threshold voltage of ECL circuitry. The relatively small voltage differential of the ECL logic levels, however, results in a degradation of the operating speed of the CMOS circuit. In addition, the duty cycle of the circuit output signal may vary due to variations in the threshold level at the input.